The inventive concept relates to semiconductor devices and more particularly to Complementary Metal Oxide Semiconductor (CMOS) image sensors. Certain embodiments of the inventive concept relate to sense amplifiers including a negative capacitance circuit. Such sense amplifiers may be used within CMOS image sensors and related apparatuses to better facilitate the high speed output of data at reduced bit error rates.
Conventional CMOS image sensors usually couple a multiplicity of data storage elements (e.g., 1-bit Static Random Access Memory (SRAM) elements) to one or more data channels connecting a sense amplifier. Each channel may include relatively long signal line(s) that connect respectively selected data storage elements to the sense amplifier. The number of connected data storage elements, the bandwidth of the channel and the length of the constituent signal line(s) will affect the speed with which data may be coherently communicate to the sense amplifier. Accordingly, attempts to increase the rate at which data is output through a CMOS sense amplifier must address such interrelated factors as channel width and signal transmission characteristics and limitations in view of an acceptable bit error rate, etc. And all these factors must be weighed against the permissible size and power consumption characteristics of the CMOS image sensor and constituent component parts.